ESS designs sensor components for commercial high-end applications. ESS designs both the capacitive MEMS element and the interfacing ASIC. The integrated circuit to be simulated is signal conditioning electronics for accelerometer and pressure sensors. An important step in the design process is parasitic extraction for the estimation of the parasitic capacitance of the front-end electronics. Currently, ESS’s design process by passes parasitic extraction and employs rules of thumb that will ensure minimal crosstalk. The commercially available parasitic extractors are very expensive.
- Enable ESS to either improve performance of their signal conditioning electronics, if parasitic effects turn out to be important, or insert a reference capacitor on-chip, since in the case that parasitic effects turn out to be negligible it will be possible to free on-chip area for the capacitor by packing more densely existing metal lines.
- Enable the end user to access computational Cloud engineering services needed for improving: products / reliability assessment / compliance with requirements / predictability of product behaviour.
- Allow HELIC to offer products / services on the Cloud, through a new business model.
- Increase the affordability of HELIC’s products and services.
- Complement the existing experiments in manufacturing and mechanical large scale design by focusing on nanoscale component design for sensor chip technology which finds application in robotics, NDT (non-destructive testing), automotive etc.
- HELIC and ATHENA work together in Netlist reduction by numerical linear algebra techniques, so as to preserve accuracy, as well as in parallelization of matrix operations.
Potential benefits and impact
By using their software in the cloud HELIC could expand their client base to SMEs who cannot afford a full annual license. An added benefit of cloudifying the software is that it will serve as a vehicle to approach academia with free services in order to gain brand recognition, receive user feedback and enter new collaborations . A technical benefit will be optimised algorithms for faster software to reach a competitive advantage.
ESS (and other SMEs) will have access to high quality chip-design tools and can optimise chip size with impact in cost savings and added functionality. Anticipated benefits in terms of performance include higher resolution and reliability due to less noise in the signal, while an example of added functionality is device interoperability. In all, this is an opportunity to achieve overall improvements in the final product and gain a competitive edge.
Helic S.A.- Greece, European Sensor Systems -ESS- (Greece), ATHENA Research & Innovation Center (Greece), Arctur računalniški inženiring d.o.o. (Slovenia)
Electrical & optical equipment
Modelling & Simulation