Computational Methods and Algorithms on HPC Platforms and Accelerators - CompHPC 2017
With the advent of multi-core CPUs and manycore accelerators such as GPUs and FPGAs, mainstream processor chips and computers are now parallel computational systems with their parallelism continuously scaling according to Moore's law. Software implementations designed for these systems need to address issues that deal with memory latency, communication and power consumption. The challenge is to develop numerical algorithms that are scalable in order to leverage the increasing number of processor cores and harness the available computational power. Addressing such a challenge is crucial for engineers because, as new materials and new applications emerge, traditional design rules and conventional testing methods become insufficient and of high cost, necessitating the use of computational methods and their implementation on such parallel computational systems.
The aim of the conference is to gather academic researchers and industrial partners involved in the development and application of numerical procedures applied in engineering problems, implemented in contemporary massively parallel systems including but not limited to GPUs and FPGAs. This will greatly facilitate the exchange of ideas in topics of mutual interest and to serve as a platform for establishing links among research groups in Europe and worldwide.